Integrated circuits (microchips), are designed, modeled and simulated in more than 20 discrete design steps. Near the final steps where the design evolves to a physical layout, it is important that the models of the chip used in simulations are realistic, accounting for the electromagnetic behavior of the actual materials and geometries, so as to avoid performance shortcomings due to unforeseen, so called “parasitic”, electrical and electromagnetic properties of the various chip components.
- Use of cloud version of Helic’s modeling software to derive realistic chip models and free-up space on the chip
- Use of the freed space to add new on-chip components and thus broaden the market opportunities for the chip
- Enable the particular innovation by using an on-cloud version of Helic’s software
- Reduce chip de-risking time by 1.5 weeks for the particular 12 week exercise (10 percent time saving)
In this particular experiment Helic’s cloudified RaptorX parasitics extraction software, helped ESS modify its MEMS chip design and add interfaces for a broader range of devices, while maintaining the same chip dimensions and cost. In particular ESS:
- freed 5 percent off the chip area, by placing closer together certain on-chip transmission lines, whilst maintaining achieved levels of performance,
- utilized the freed area to add components and extend the ASIC’s ability to interface with all combinations of capacitive sensor structures,
- ensure that is no crosstalk on the chip, without manually implementing pre-modeled generic foundry components.
In the present demonstration, since only a small, but crucial, part of the chip was extracted, the improvement due to the small extraction time is negligible. However, if one takes into account the time saved compared to the time needed to utilize alternative strategies to extraction (substitution of metal lines with pre-modeled METAL RESISTOR CELLS and utilization of conservative rules on physical design), then the overall project’s duration benefit is around 10 percent. In terms of production costs reduction, were ESS to directly reduce chip area by 5 percent without adding the extra components, they would achieve a cost saving of approximately 5 percent on wafer costs. For an indicative cost of 0.8 dollars/chip, savings would be in the order of 40,000 dollars (36,700 euros) for 1 million pieces. It must be stressed however, that in this particular instance ESS benefits not from dollar savings on Si area, but on added functionality!
In terms of software license fees savings, should ESS decide to introduce the SaaS version of RaptorX in its design flow and employ it on crucial chip’s blocks, the cost reduction for ESS’s use of the cloud’s extraction scheme vs the standard extraction scheme is in the order of whopping 80-90 percent. This would result in savings compared to the overall EDA tools licensing cost that ESS utilizes, of 25-30 percent, which may be up to 40,000 euros per year.
Additional financial benefits for designers include savings on expensive tape-outs (chip prototypes) and subsequent measurements which show chip misbehavior due to unaccounted parasitics in the model avoiding losses incurred by getting into the market with underperforming and thus underpriced chips, in order to meet customer timescales. Such savings vary widely, depending on chip technology, volume and application area.